Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/System Verilog)OverviewAt Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital infrastructure. Specialized in cutting-edge RISC-V systems and backed by major innovation initiatives, our partner is assembling a world-class engineering team in Barcelona. They are now seeking aSenior Verification Engineerwith expertise in System Verilog and UVM to ensure their next generation of high-performance silicon meets the highest quality ntract:Permanent – Internal team of our partnerWhy This Role Is UniqueJoin the forefront of Europe’s semiconductor revolution in CPU design and verification.Verifycutting-edge RISC-V processorsdestined for high-performance computing applications.Use the latestadvanced verification methodologies(UVM, formal verification) on complex, modern microarchitectures.Full-cycle ownership– contribute from block-level verification to full system validation.Influence design quality from day one;

your work directly impacts first-silicon success.What You’ll Be DoingDevelop and maintainUVM-based testbenchesfor complex digital designs (CPU cores, So C blocks).Define and implement comprehensiveverification plans, covering all features and corner cases.Write and run directed andconstraint-random teststo validate functionality and performance.Implement checkers and monitors in System Verilog to verify correctness of microarchitectural features.Execute extensive simulations and regression suites;

analyze waveform dumps to debug failing tests.Usecoverage-driven verification(functional and code coverage) to measure progress and target gaps.Applyformal verificationtechniques to prove critical properties and catch corner-case bugs.Automate workflows with scripting (Python/Perl/Bash/TCL)



for regression management and result llaborate closely with design and RTL teams to review specifications, discuss bugs, and drive fixes to closure.What You BringMaster’s or Ph D in Electronic Engineering, Computer Engineering, or related field.8+ yearsof experience in digital design verification.Proven expertise inSystem VerilogandUVMfor complex ASIC/So C verification.Strong scripting skills (Python, Perl, Bash, or Tcl) to automate verification flows and data analysis.Hands-on experience with simulation tools (e.G., Model Sim, VCS, Xcelium) and waveform debugging.Familiarity with coverage metrics andcoverage closurestrategies.Knowledge offormal verificationtools/methods (property checking, equivalence checking) is a plus.Experience verifying bothblock-level modulesand fullsystem-level integrations.Proficiency with version control systems (Git, SVN) in collaborative engineering projects.Excellent problem-solving abilities andattention to detail– able to root-cause intricate bugs.Strong communication and teamwork skills, collaborating effectively with cross-functional teams.English fluency (C1 or higher).What’s in It for YouFlexible working hours– Focus on outcomes, not just petitive compensation– Recognizing your expertise and impact.Learning-driven culture– Work with top-tier engineers on cutting-edge projects;

continuous growth encouraged.Visa sponsorship– Open to international talent;

relocate to a vibrant tech hub.Candies, coffee, and free Spanish lessons– Enjoy a welcoming office culture while settling into life in Barcelona.Barcelona HQ– Where tech innovation meets Mediterranean lifestyle.Ready to Build the Future of Chips in Europe?If you’re passionate about verification and want to play a key role in one of Europe’s most exciting deep-tech projects, we want to hear from you.Apply now— Akuaro is exclusively managing this hiring process for our partner. Let’s connect and explore this opportunity together.

📌 Senior Verification Engineer – Drive Quality In Next‑gen Risc‑v Cpus (Uvm/Systemverilog) (Barcelona)
🏢 Akuaro
📍 Barcelona