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Principal Physical Design Engineer

Role Overview
The Principal Physical Design Engineer is a senior technical leader responsible for end-to-end physical implementation and signoff of complex SoCs across advanced technology nodes. The role combines hands-on RTL-to-GDSII expertise, design convergence, and team leadership to deliver high-quality silicon in partnership with Design, DFT, Verification, CAD, and signoff teams.

Key Responsibilities
Own RTL-to-GDSII implementation, including floorplanning, CTS, routing, equivalence checking, ECO implementation, and STA closure. Apply a strong working knowledge of SDC timing constraints and timing closure to review implementation results and provide informed feedback to the Physical Design and Design teams. Apply hands-on experience with Cadence and or Synopsys based physical design flows to drive implementation, optimisation, flow debugging, and signoff activities. Drive setup and hold timing closure, IR/EM analysis, congestion resolution, and physical verification to achieve PPA and quality targets.



Lead signoff activities, including multi-mode multi-corner STA, DRC/LVS physical verification, and power analysis. Provide leadership for a geographically distributed Physical Design team, overseeing planning, execution, and issue resolution while collaborating across locations with design teams and project leads to manage priorities, mitigate risks, and meet key project milestones. Drive project risk management by identifying, evaluating, and mitigating technical risks and dependencies, providing critical input from a physical design perspective, and clearly communicating trade-offs, status, and recommendations to stakeholders and leadership.
Qualifications
B.Tech., M.Tech., or higher qualification in Electrical or Electronics Engineering, or an equivalent discipline. 10+ years of physical design experience, with successful tape-outs on advanced technology nodes. Hands-on experience with indus

📌 Principal Physical Design Engineer (Valencia)
🏢 Analog Devices
📍 Valencia