Semidynamics is seeking a seasoned Low Power Verification Lead to ensure UPF integrity across RTL, synthesis, and physical design for hierarchical blocks.
You will own VCLP sign-off and drive convergence of low-power intent throughout the design flow.Collaborating with RTL, Synthesis, DFT and PD teams, you will develop automation, debug VCLP issues, and strengthen methodologies to deliver robust, scalable VCLP sign-off across projects.
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📌 Low-Power Verification Lead: Vclp (España)
🏢 Semidynamics
📍 España
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