Semidynamcis is seeking a Senior LPDDR5X Controller/PHY First-Silicon Bring-Up Engineer to support reconstruction, implementation and physical qualification of the LPDDR5X Controller/PHY initialization and training flow, taking controlled verification collateral through to deterministic first-silicon execution and failure diagnosis. Required experience * Demonstrable DDR/LPDDR post-silicon bring-up experience; LPDDR5/LPDDR5X experience is strongly preferred. * Strong understanding of memory-controller and PHY initialization, DRAM mode registers, timing configuration and frequency operating points. * Hands-on experience with PHY initialization firmware, mailbox/status flows, calibration and training procedures. * Experience diagnosing training failures and separating controller, PHY, DRAM, clock, reset and board-level causes. * Low-level C/C++ firmware development and direct MMIO/register access. * Ability to translate ordered verification sequences into deterministic executable firmware with readback, polling and bounded timeout handling.
* Understanding of memory read/write sanity testing and the transition from training PASS to a usable memory configuration. * Practical laboratory experience during physical first-silicon memory bring-up. Strongly preferred * Direct experience with Cadence DDR/LPDDR Controller and PHY IP. * Experience with Cadence PHY firmware/training flows or comparable commercial DDR PHY solutions. * LPDDR5X frequency switching, training checkpoints and known-good configuration capture. * Experience with first CPU-visible bandwidth measurements and controlled memory-performance evidence. * Experience correlating verification traces, register databases and physical-silicon results. Expected responsibilities * Review existing DDR verification collateral and identify the authoritative initialization/training sequence. * Help convert the sequence into maintainable low-level C/C++ code rather than a blind register replay. * Define register access wid