The RoleAs a Senior Formal Verification Engineer, you will contribute to defining and leading the formal verification strategy for our systems.ResponsibilitiesWork closely with system architects and design team to establish formal verification environment and settingGuide the use of formal verification so that correct formal techniques are used appropriately to improve efficiency of IP and SoC level verificationContribute to define Formal Verification MethodologiesProduce IP level, subsystem level and chip level test plans based on Design documents and interaction with design and architecture teamsWrite and debug System Verilog assertionsAnalyze coverage data and working with Design teams to address coverage holesContribute to developing framework for running regressions and debugging regression failuresSupport integration of design in higher-level subsystem including test planning, test vector delivery,
and debug of test vectors at the integration levelScripting/Automation skills for improving workflows along with the usage of most advanced AI techniquesParticipate in project reviewsProvide supervision/guidance to other team membersRequired QualificationsMaster's degree in relevant fieldMin 5 years of experience in relevant field of Formal VerificationA deep understanding of formal verification, including applications, verification of algorithms, protocols, and application of formal verification at SoC levelMade significant contributions in the use of formal verification and be able to guide formal verification development into new areasFormal tools, System Verilog, SV Assertions and Assumptions, Scripting skillsApps in formal tools (Low power, X-prop, Connectivity checking, Register Map Verification)Design debug, Deep bug huntingDesign knowledge of CPU, NoC/Interconnect, Memory Controllers, CachesSoft SkillsTeam player, able to work with multiple cultures both on site and remotelyAutonomous and adaptable is mandatoryWhat We Offer?The opportunity to build a cloud AI