Role Overview As a low power verification lead, you will play a key role in ensuring low-power intent integrity across the design lifecycle. You will be responsible for VCLP signoff, ensuring seamless convergence between RTL, synthesis, and physical design stages for hierarchical designs. Key Responsibilities * Understand low power specs and write UPF for hierarchical designs * Validate low-power architecture, UPF constraints, and intent across multiple domains. * Debug VCLP failures, including issues arising from clock gating, retention, isolation, and level shifters * Ensure convergence of UPF across synthesis, place-and-route, and ECO cycles * Work closely with RTL, Synthesis, DFT,



and Physical Design teams to resolve low power issues * Develop automation scripts and improve methodology for VCLP sign-off Technical Skills * Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related discipline * 7+ years of experience in low power methodologies and low power static verification using VCLP * Strong understanding of low-power design concepts (UPF) and methodologies * Experience with synthesis, netlist optimizations, and equivalence debugging * Proficiency in scripting languages such as TCL, Python, or Perl * Experience with hierarchical Sub system level VCLP flows Preferred Qualifications * Familiarity with DFT concepts and scan impact on UPF and UPF checks * Knowledge of STA and Physical Design interactions impacting UPF Success in This Role Looks Like * Clean VCLP sign-off * Fast turnaround time in debugging and resolving VCLP/UPF issues * Robust, scalable VCLP methodologies across projects * Strong cross-team collaboration ensuring smooth design convergence

📌 Low Power Verification Lead (Cataluña)
🏢 Semidynamics
📍 Cataluña