Job DescriptionOur partner is looking for aSenior Signal Integrity Engineerto own signal integrity across package, board and system level interconnects for advanced compute hardware.This is a senior individual contributor role with architectural influence. You will help define SI budgets and design constraints, not simply verify completed layouts, and will work closely with package, PCB, PHY, memory and system teams.Location:Barcelona, Spain, HybridLevel:SeniorResponsibilitiesOwn signal integrity from silicon package through board and system channelDefine loss, crosstalk and jitter budgetsPerform pre layout feasibility studiesGuide routing, stackup and layer assignmentRun 3D EM extraction of package and board structuresPerform statistical and time domain channel simulationOwn PCIe Gen6 channel design and compliance marginingSupport LPDDR interface timing and bus level closureDefine model quality requirements for passivity, causality and DC accuracySet SI requirements for package, OSAT and component vendorsCoordinate models with PHY, DRAM and package suppliersCorrelate simulations with VNA,



TDR and silicon measurementsSupport board bring up and SI debugAutomate analysis and post processing with PythonRequirements8+ years of signal integrity experienceBackground in high speed digital systemsStrong package level SI experience3D EM extraction experienceHFSS, SIwave, Clarity, Sigrity, Keysight or equivalentProven SerDes channel closure experiencePCIe Gen5, Gen6 or comparable interface experienceDDR5, LPDDR5, LPDDR6 or HBM experienceStrong IBIS and IBIS AMI knowledgeChannel simulation experienceAbility to analyse substrate stackups and bump mapsStrong understanding of loss, crosstalk, jitter and channel behaviourPython scripting for automation and analysisOptional / Desired2.5D, interposer or chiplet package designAdvanced substrate experienceMaterial characterisationMeasurement and simulation correlationOCP rack platform experienceHigh speed connector and backplane experiencePyAEDTscikit rfAutomated engineering workflowsWhat's in it for you?Versátil working hoursHybrid model, 4 days office, 1 day from home1 week per year working from anywhere25 days annual leave plus December 24 and 31Monthly food allowancePrivate medical insuranceRelocation bonusHousing search supportVisa support if requiredFamily relocation supportVirtual sharesLanguage classesTax incentive, subject to eligibility#J-18808-Ljbffr

📌 Senior Signal Integrity Engineer (Madrid)
🏢 Hireroo
📍 Madrid