Role summaryOwn verification of the Load/Store Unit, data cache and bus interfaces for a CPU/GPU core — the block handling memory ordering, address generation, cache/TLB interaction, forwarding, and exception handling. Contribute to drive the LSU from RTL freeze to tapeout-quality sign-off.ResponsibilitiesDefine and own the LSU verification plan: functional coverage, testplan, checkers, and closure criteriaBuild/extend UVM testbench components for LSU (drivers, monitors, scoreboards, memory models)Develop directed and constrained-random tests covering store-to-load forwarding, memory ordering (RISC-V WMO model), speculative loads, vector accesses, misaligned/split accesses, exceptions/faults, and pipeline hazardsDrive formal verification for ordering/coherence properties where simulation coverage is weakDebug RTL/testbench failures in collaboration with design; triage and root-causeTrack and close functional/code coverage; report verification status to program leadsMentor junior verification engineers; review testbench code and testplansInterface with architecture, design, and DV leads on other units to resolve cross-unit issues.Required qualificationsBS/MS in EE/CE/CS, 5+ years in ASIC functional verification.Strong SystemVerilog/UVM experience; hands‑on testbench architectureDeep understanding of memory subsystems: cache hierarchies, TLBs, memory consistency models,



load/store pipelinesKnowledge of RISC‑V ISA and privileged specification is mandatoryKnowledge of AMBA AXI4, AXI5Lite and CHI is mandatoryExperience with coverage‑driven verification and regression managementDebugging complex RTL failures using waveform tools (Verdi/DVE or similar)PreferredFormal verification experience (JasperGold or similar) applied to memory ordering/coherenceKnowledge of CPU architecture and memory execution pipelinePrior LSU, cache, or memory‑controller verification specificallyExperience with RISC‑V, ARM, or x86 memory modelsScripting (Python/Perl) for verification infrastructure and regression automationPrior team lead or mentorship experienceNice to HaveEmulation platforms (Veloce, ZeBu)Familiarity with fuzzing techniques (AFL++)Knowledge of SystemC/C++ testbenchesEssential Soft SkillsAn adversarial, gap‑seeking mindset — instinctively asks "who actually checks this?" — collaborative relationship with the whole core.Clear communication across DV, design, and software teams; writes verification plans others can follow.Why Semidynamics?Work at one of Europe's most promising deep‑tech semiconductor scale-ups.Accelerated development path.4 days per week in the Barcelona office (city center), 1 WFH day.1 week of work from everywhere in the world.Competitive package.A collaborative, technical, and growth‑oriented environment that values direct ownership and clear thinking.#J-18808-Ljbffr

📌 Senior Verification - Lsu (Load/Store Unit) And Data Cache (Madrid)
🏢 Semidynamics
📍 Madrid