As a static formal verification lead, you will play a key role in ensuring functional correctness and low-power intent integrity across the design lifecycle. You will be responsible for equivalence checking with and without UPF, ensuring seamless convergence between RTL, synthesis, and physical design stages for hierarchical designs.Key ResponsibilitiesPerform RTL-to-Gate and Gate-to-Gate equivalence checks using tools like Synopsys FormalityDebug LEC failures, including issues arising from clock gating, retention, isolation, and level shiftersEnsure convergence of LEC across synthesis, place-and-route, and ECO cyclesWork closely with RTL, Synthesis, DFT,



and Physical Design teams to resolve design mismatchesHandle ECO validation and ensure equivalence closure post-design changesDevelop automation scripts and improve methodology for LEC sign-offTechnical SkillsBachelor's or Master's degree in Electrical/Electronics Engineering or related discipline7+ years of experience in Formal Verification/LECStrong expertise in tools like Synopsys Formality/VC LPUnderstanding of low-power design concepts (UPF)Experience with synthesis, netlist optimizations, and equivalence debuggingProficiency in scripting languages such as TCL, Python, or PerlExperience with hierarchical Sub system level LEC flowsRequirementsPreferred QualificationsFamiliarity with DFT concepts and scan impact on equivalenceKnowledge of STA and Physical Design interactions impacting LECSuccess in This Role Looks LikeClean LEC sign-off with zero functional mismatchesFast turnaround time in debugging and resolving equivalence issuesRobust, scalable LEC methodologies across projectsStrong cross-team collaboration ensuring smooth design convergence#J-18808-Ljbffr

📌 Formal Verification Lead (Madrid)
🏢 Semidynamics
📍 Madrid