We are looking for a Design Verification Engineer to support gate-level simulation (GLS) and hardware emulation activities for our AI chip design and verification teams. In this role, you will help ensure silicon correctness by validating post-synthesis netlists, debugging timing and reset issues, and enabling large-scale emulation of SoC designs prior to tapeout. This is a hands-on role requiring close collaboration with RTL design, DFT, physical design, and firmware teams.Key Responsibilities- Set up, run, and debug gate-level simulations (GLS) for functional, timing (SDF back-annotated), and low-power verification across multiple design blocks and full-chip levels.- Support hardware emulation platforms Siemens Veloce including design compilation, bring-up, debug, and regression management.- Debug mismatches between RTL and gate-level simulation results, including X-propagation, timing violations, glitches, and clock/reset domain issues.- Develop and maintain testbenches, scripts, and flows to automate GLS and emulation compile/run cycles.- Collaborate with DFT engineers to validate scan, ATPG patterns, and BIST in gate-level and emulation environments.- Work with physical design and STA teams to resolve SDF annotation, timing exceptions, and back-annotated simulation discrepancies.- Bring up emulation models for pre-silicon software/firmware validation and performance profiling.- Triage and root-cause simulation/emulation failures, track bugs, and drive issues to closure with cross-functional teams.- Optimize simulation and emulation runtimes, capacity, and compile turnaround for large SoC designs.- Maintain documentation of GLS/emulation methodologies, flows,



and known issues.Requirements- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.- 3+ years of experience in ASIC/SoC design verification, with direct exposure to gate-level simulation.- Hands-on experience with at least one hardware emulation platform (Palladium, ZeBu, Veloce) or FPGA-based prototyping.- Strong understanding of digital design fundamentals: clocking, reset strategies, low-power design (UPF/CPF), and STA concepts- Proficiency with Verilog/SystemVerilog and simulation tools (e.G., VCS, Xcelium, Questa).- Experience with SDF back-annotation and timing-accurate gate-level simulation- Scripting skills in Perl, Python, or TCL for flow automation and debug.- Familiarity with version control (Git/Perforce) and job scheduling systems (LSF/Grid).- Strong debugging skills and ability to work independently on complex, ambiguous problems.Preferred Qualifications- Experience with DFT flows (scan insertion, ATPG, MBIST) and their validation in GLS/emulation.- Exposure to UVM-based verification methodologies.- Experience bringing up firmware or software on emulation platforms.- Familiarity with low-power verification (UPF-based simulation, power-aware GLS).- Experience working on large multi-million gate SoC designs.- Knowledge of physical design flows and their interaction with timing closureWhy Semidynamics?- Work at one of Europe’s most promising deep-tech semiconductor start up - from silicon to systems - Semidynamics.- Accelerated development path.- 4 days per week in the Barcelona office (city center), 1 day WFH.- 1 week of work from everywhere in the world.- Competitive package.- A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.#J-18808-Ljbffr

📌 Design Verification Engineer – Gls & Hardware Emulation (Barcelona)
🏢 Semidynamics
📍 Barcelona