Job DescriptionOur partner is looking for aLow Power Verification Leadto ensure low power intent is implemented and verified correctly across the full design flow.The role focuses on VCLP signoff, UPF development, hierarchical low power verification and convergence between RTL, synthesis and physical design.Location:Barcelona, Spain, HybridLevel:SeniorResponsibilitiesDevelop and maintain UPF for hierarchical designsValidate low power architecture and intent across multiple power domainsDebug VCLP failures related to clock gating, retention, isolation and level shiftersEnsure UPF convergence across synthesis, place and route, and ECO cyclesWork closely with RTL, Synthesis,



DFT and Physical Design teamsResolve low power issues across implementation stagesDevelop automation scripts for VCLP signoffImprove low power verification methodology and scalabilityRequirements7+ years of low power verification experienceStrong hands on experience withVCLPStrong knowledge ofUPFHierarchical low power verification experienceUnderstanding of retention, isolation, level shifters and clock gatingExperience with synthesis, netlist optimization and equivalence debuggingTcl, Python or Perl scriptingBachelor or Master degree in Electrical Engineering, Electronics or related fieldOptional / DesiredRISC V experienceDFT and scan interaction with UPFSTA interaction with low power intentPhysical Design interaction with UPFExperience improving low power signoff methodologyWhat’s in it for you?Versátil working hoursHybrid model, 4 days office, 1 day from home1 week per year working from anywhere25 days annual leave plus December 24 and 31Monthly food allowancePrivate medical insuranceRelocation bonusHousing search supportVisa support if requiredFamily relocation supportVirtual sharesLanguage classesTax incentive, subject to eligibility#J-18808-Ljbffr

📌 Low Power Verification Lead (Madrid)
🏢 Hireroo
📍 Madrid