Job DescriptionOur partner is looking for aSenior Verification Engineerto own verification of the Load/Store Unit, data cache and related bus interfaces within a processor core.The role covers memory ordering, cache and TLB interaction, address generation, forwarding, speculative execution, vector accesses, exceptions and pipeline hazards. You will own the verification scope from planning through sign off, working closely with architecture, RTL and other verification teams.Location:Barcelona, Spain, HybridLevel:SeniorResponsibilitiesOwn the LSU verification plan, test strategy and closure criteriaBuild and extend UVM testbench components, including drivers, monitors, scoreboards and memory modelsDevelop directed and constrained random testsVerify store to load forwarding and memory orderingVerify speculative loads and vector memory accessesCover misaligned and split accesses, exceptions and faultsVerify cache, TLB and load/store pipeline interactionsDrive functional and code coverage closureManage regressions and analyze verification resultsApply formal verification to ordering or coherency properties where requiredDebug RTL and testbench failures and drive root cause analysisResolve cross unit verification issues with architecture and design teamsReview verification code and mentor junior engineersRequirements5+ years of ASIC functional verification experienceStrong SystemVerilog and UVMHands on testbench architecture experienceDeep understanding of LSU, caches, TLBs and memory subsystemsStrong knowledge of memory consistency and load/store pipelinesRISC V ISA and privileged specificationAXI4, AXI5 Lite and CHICoverage driven verificationFunctional and code coverage closureRegression managementStrong RTL debugging skillsVerdi, DVE or similar waveform toolsBS or MS in Electrical Engineering, Computer Engineering, Computer Science or related fieldOptional / DesiredFormal verification using JasperGold or similarCPU architecture and memory execution pipeline experiencePrior LSU, cache or memory controller verificationRISC V, ARM or x86 memory modelsPython or Perl scriptingTechnical mentoring experienceVeloce or ZeBuAFL++ or other fuzzing techniquesSystemC or C++ testbenchesWhat’s in it for you?Adaptable working hoursHybrid model, 4 days office, 1 day from home1 week per year working from anywhere25 days annual leave plus December 24 and 31Monthly food allowancePrivate medical insuranceRelocation bonusHousing search supportVisa support if requiredFamily relocation supportVirtual sharesLanguage classesTax incentive, subject to eligibility#J-18808-Ljbffr

📌 Senior Verification Engineer, Lsu And Data Cache (Madrid)
🏢 Hireroo
📍 Madrid