Semidynamics in Barcelona, Spain seeks a static formal verification lead to ensure functional correctness and low-power intent across the design lifecycle. You will drive RTL-to-Gate and Gate-to-Gate equivalence checks, debug LEC issues, and ensure seamless convergence between RTL, synthesis, and physical design for hierarchical designs.The role requires 7+ years in Formal Verification/LEC, expertise with Synopsys Formality/VC LP, and strong scripting skills (TCL/Python/Perl).#J-18808-Ljbffr
📌 Lead Formal Verification - 4-Day Week, Barcelona Office (Madrid)
🏢 Semidynamics
📍 Madrid
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