Job DescriptionOur partner is looking for aDFT Engineerto support DFT implementation, test development and production readiness for complex SoC and SiP designs.You will work across pre silicon and post silicon stages, collaborating with design, validation, packaging, operations, external IP providers and EDA vendors. The role focuses on improving testability, manufacturability, test coverage, yield and production quality across advanced semiconductor programs.Level:MidLocation:Barcelona, Spain, HybridResponsibilitiesDefine and implement DFT architecturesInsert and validate scan chains, BIST and JTAGSupport DFT integration across SoC and SiP designsDevelop silicon, package and system level test strategiesDevelop automated production and characterization test solutionsImprove test coverage, test time, cost and production efficiencySupport post silicon test optimization, silicon debug and yield analysisWork with design and validation teams to resolve DFT related issuesCollaborate with packaging, operations, IP providers and EDA vendorsContribute to DFT methodology and process improvementsSupport production readiness and test quality through development and rampRequirements4+ years of DFT, silicon test or related semiconductor experienceTessent and SSN experienceExperience integrating Tessent or SSN methods with advanced node EDA flowsExperience with SoC or SiP tape outsStrong understanding of scan chains,



BIST and JTAGDFT architecture and implementation experiencePost silicon test optimization and yield analysisExperience defining production test strategiesUnderstanding of silicon characterization and test coverageSystemVerilog and VerilogShell, Tcl or Python scriptingAbility to work across design, validation and manufacturing teamsBachelor, Master or PhD in Electrical Engineering, Computer Engineering or related fieldPreferred / Valued KnowledgeRISC V architecture, especially within SoC, RTL, verification, DFT, Physical Design, firmware, software, PCIe, DDR or related hardware environmentsExperience with advanced semiconductor nodesProduction test and high volume manufacturing exposureExperience improving DFT methodology, test cost or yieldFamiliarity with chiplet based designsWhat’s in it for you?Our partner offers an opportunity to work on advanced semiconductor programs in Barcelona, with strong technical ownership and career growth.4 days per week in the Barcelona office, 1 day from homeFlexible working hours1 week per year working from anywhere25 days annual leave plus December 24 and 31€150 monthly food allowancePrivate medical insuranceRelocation supportHousing search assistanceVisa support where requiredRelocation support for familyVirtual sharesLanguage classesTax support, subject to eligibility#J-18808-Ljbffr

📌 Dft Engineer - Mid (Madrid)
🏢 Hireroo
📍 Madrid