Job DescriptionOur partner is expanding its semiconductor engineering team and is looking for an experiencedSTA & Synthesis Lead Engineerto own synthesis, static timing analysis, timing closure and design optimization across complex digital designs.You will work from RTL through implementation and sign off, driving synthesis quality, PPA optimization and timing convergence across hierarchical and top level designs. The role requires close collaboration with RTL, DFT and Physical Design teams to identify bottlenecks, resolve implementation issues and ensure robust timing closure.Level:SeniorLocation:Barcelona, Spain, HybridResponsibilitiesDrive physical aware RTL to gate synthesis at block and top levelOptimize designs for power, performance and areaAnalyze synthesis results and identify optimization opportunitiesDevelop, validate and debug SDC constraintsDefine clocks, generated clocks, I/O constraints and timing exceptionsManage false paths, multicycle paths and case analysisPerform MMMC static timing analysis and timing sign offAnalyze setup, hold, recovery, removal and clock gating checksInvestigate critical paths and timing bottlenecksGenerate, implement and validate timing and functional ECOsResolve post placement and post route timing issuesSupport functional, scan and DFT timing modesWork with RTL,



DFT and Physical Design teams to improve design convergenceImprove synthesis and timing closure methodologyRequirements7+ years of hands on synthesis and STA experienceStrong logic and physical synthesis experiencePPA optimization across complex digital designsDeep knowledge of STA and MMMC analysisStrong SDC development, validation and debuggingTiming closure across block, subsystem and top level designsECO implementation and validationStrong knowledge of setup, hold and clock related timing analysisUnderstanding of clock skew, latency, jitter, uncertainty and variationKnowledge of PVT conditions and their impact on timingExperience withPrimeTime, Fusion Compiler, Formality and VCLPExperience with advanced semiconductor nodes, ideally3nm or belowHierarchical and top level STA experienceExperience with synthesis, parasitic data and SDF based timing analysisStrong debugging and problem solving skillsOptional / DesiredRISC V architecture experienceDFT and scan timingCTS and clock tree related timing issuesHierarchical physical synthesisFormal equivalence checkingAdvanced node SoC experienceExperience working across RTL, synthesis, STA and Physical Design sign offWhat’s in it for you?Our partner offers an opportunity to work on advanced semiconductor development in Barcelona, with significant ownership of synthesis and timing methodology.4 days per week in the Barcelona office, 1 day from homeFlexible working hours1 week per year working from anywhere25 days annual leave plus December 24 and 31Monthly food allowancePrivate medical insuranceRelocation supportHousing search assistanceVisa support where requiredVirtual share planLanguage classesTax support, subject to eligibility#J-18808-Ljbffr

📌 Sta & Synthesis Lead Engineer (Madrid)
🏢 Hireroo
📍 Madrid