Senior Verification Engineer – Drive Quality in Next‑Gen RISC‑V CPUs (UVM/SystemVerilog)OverviewAt Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what’s possible in high-performance computing and digital infrastructure. Specialized in cutting-edge RISC-V systems and backed by major innovation initiatives, our partner is assembling a world-class engineering team in Barcelona. They are now seeking aSenior Verification Engineerwith expertise in SystemVerilog and UVM to ensure their next generation of high-performance silicon meets the highest quality standards.Contract:Permanent – Internal team of our partnerWhy This Role Is UniqueJoin the forefront of Europe’s semiconductor revolution in CPU design and verification.Verifycutting-edge RISC-V processorsdestined for high-performance computing applications.Use the latestadvanced verification methodologies(UVM, formal verification) on complex,



modern microarchitectures.Full-cycle ownership– contribute from block-level verification to full system validation.Influence design quality from day one; your work directly impacts first-silicon success.What You’ll Be DoingDevelop and maintainUVM-based testbenchesfor complex digital designs (CPU cores, SoC blocks).Define and implement comprehensiveverification plans, covering all features and corner cases.Write and run directed andconstraint-random teststo validate functionality and performance.Implement checkers and monitors in SystemVerilog to verify correctness of microarchitectural features.Execute extensive simulations and regression suites; analyze waveform dumps to debug failing tests.Usecoverage-driven verification(functional and code coverage) to measure progress and target gaps.Applyformal verificationtechniques to prove critical properties and catch corner-case bugs.Automate workflows with scripting (Python/Perl/Bash/TCL) for regression management and result analysis.Collaborate closely with design and RTL t

📌 Senior Verification Engineer – Drive Quality In Next‑gen Risc‑v Cpus (Madrid)
🏢 Akuaro
📍 Madrid