Senior Engineer, Digital Design Engineering (Madrid)

Senior Engineer, Digital Design Engineering (Madrid)

09 oct
|
1120 Ad Spain
|
Madrid

09 oct

1120 Ad Spain

Madrid

About Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI) is a general semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.Analog.Com and on LinkedIn and X.Senior Digital Design Engineer ResponsibilitiesThis position will involve many of the following tasks.FPGA prototyping of designDevelopment of models & self checking mechanisms for FPGA HW & S/WCodesignArchitectural design and specification of blocksVerilog/SystemVerilog RTL designInteraction with customer and stakeholdersDesign to meet timing, area, low‑power, DFT,



manufacturing test and timing targets for marketAll aspects of design work including interaction with verification and analog teamInteraction with implementation team to convert RTL to siliconDefining timing constraints and performing static timing analysisWorking with architecture and design teams to determine functionality protocolsQualificationsBachelor's or Master's degree, in Engineering (Electronic Engineering) or equivalentArchitectural design and specification of complex systems, especially in system on chip with processorsDeep knowledge of FPGA development flow, FPGA modelling, Verilog/SystemVerilog RTL design - with emphasis on AHB, AXI protocols and processor architecture on ARM coresDesign to meet timing, area, low‑power, manufacturing test and timing targets for marketAll aspects of design work including interaction with verification and analog teamInteraction with implementation team to convert RTL to siliconWorking with architecture and design teams to determine functionality protocolsAbility to work well in a div

📌 Senior Engineer, Digital Design Engineering (Madrid)
🏢 1120 Ad Spain
📍 Madrid

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