Job Description

Our partner is looking for aSenior DDR Design Engineerto design, develop and integrate high performance memory subsystem solutions for advanced semiconductor products.

You will work closely with architecture, RTL, verification and implementation teams on memory controller design, interface integration, timing and validation.

The role requires strong ownership of memory subsystem development and the ability to support designs from architecture through implementation and tape out.

Location: Barcelona, Spain, Hybrid

Level: Senior

Responsibilities

Design and integrate DDR or HBM memory subsystems

Develop and integrate memory controllers within SoC environments

Implement and review RTL using Verilog or VHDLWork with AXI based interfaces and system integration

Translate architecture requirements into robust memory subsystem designs

Apply timing constraints and support timing analysis and closure

Perform block level testing and validation

Debug memory subsystem and interface issues

Collaborate with architecture, RTL and verification teams

Support integration through implementation and tape out

Contribute to design reviews and technical decisions

Requirements8+ years of relevant industry experience





Strong DDR or HBM memory experience

Proven memory controller design or integration experience

Strong knowledge of AXI protocolRTL design using Verilog or VHDLExperience with timing and timing constraints

Block level testing and validation

Understanding of SoC memory subsystem integration

Strong debugging and problem solving skills

Ability to work across architecture, RTL and verification teams

Optional / DesiredRISC V architecture experience

Master or PhDPython, Perl, Bash or Tcl

Git or SVNParticipation in2 successful tape outs

Experience with complex SoC memory subsystems

Experience supporting timing closure and integration

Broader knowledge of memory architecture and system performance

What’s in it for you?
Adaptable working hours

Hybrid model, 4 days office, 1 day from home1 week per year working from anywhere25 days annual leave plus December 24 and 31Monthly food allowance

Private medical insurance

Relocation bonus

Housing search support

Visa support if required

Family relocation support

Virtual shares

Language classes

Tax incentive, subject to eligibility#J-18808-Ljbffr

📌 Ddr Design Engineer (Madrid)
🏢 Hireroo
📍 Madrid