Our partner is expanding its semiconductor engineering team and is looking for an experienced STA & Synthesis Lead Engineer to own synthesis, static timing analysis, timing closure and design optimization across complex digital designs.
You will work from RTL through implementation and sign off, driving synthesis quality, PPA optimization and timing convergence across hierarchical and top level designs. Level: Senior
Barcelona, Spain, Hybrid
Optimize designs for power, performance and area
Manage false paths, multicycle paths and case analysis
Perform MMMC static timing analysis and timing sign off
Resolve post placement and post route timing issues
PPA optimization across complex digital designs
~ Deep knowledge of STA and MMMC analysis
~ Strong knowledge of setup, hold and clock related timing analysis
~ Experience with synthesis, parasitic data and SDF based timing analysis
~ What’s in it for you?
4 days per week in the Barcelona office, 1 day from home
~ Adaptable working hours
~Private medical insurance
~ Relocation support
~ Visa support where required
~ Virtual share plan
~ Tax support, subject to eligibility

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