05 oct
|
Analog Devices
|
Valencia do Sil
05 oct
Analog Devices
Valencia do Sil
Analog Devices, Inc. is seeking a Senior Physical Design Engineer to own end-to-end physical implementation and signoff of digital blocks and So Cs in Valencia. You will collaborate with a distributed engineering team to deliver high-quality RTL-to-GDSII results and drive design closure. You should have hands-on experience with Cadence or Synopsys flows, and a strong background in timing, DRC/LVS, and floorplanning. Excellent communication and ownership are required. #J-18808-Ljbffr
📌 Senior physical design engineer: rtl-to-gdsii & timing (Valencia do Sil)
🏢 Analog Devices
📍 Valencia do Sil