Our partner is looking for a Formal

Verification Lead to drive equivalence checking and formal signoff across RTL, synthesis and physical implementation stages. The role focuses on RTL to Gate and Gate to Gate equivalence, low power intent, ECO validation and methodology improvement across hierarchical designs.

Location: Barcelona, Spain, Hybrid Level:

Senior Responsibilities Perform RTL to Gate and Gate to Gate equivalence checks Drive LEC signoff using Synopsys Formality or similar tools Debug mismatches related to clock gating, retention,

isolation and level shifters Validate equivalence across synthesis,

place and route, and ECO cycles Support equivalence checking with and without UPF Resolve design mismatches with RTL, Synthesis,



DFT and Physical Design teams Validate ECO changes and drive equivalence closure Develop scripts and improve formal verification methodology Requirements 7+ years of Formal Verification / LEC experience Strong Synopsys Formality / VC LP expertise RTL to Gate and Gate to Gate equivalence Hierarchical LEC flows UPF and low power concepts Synthesis and netlist optimization knowledge

Equivalence debugging Tcl, Python or Perl Bachelor or Master degree in Electrical Engineering, Electronics or related field Optional /

Desired RISC V experience DFT and scan impact on equivalence STA interaction with LEC Physical Design interaction with formal signoff Experience improving scalable LEC methodology What’s in it for you? Versátil working hours Hybrid model, 4 days office, 1 day from home 1 week per year working from anywhere 25 days annual leave plus December 24 and 31 Monthly food allowance Private medical insurance Relocation bonus Housing search support Visa support if required Family relocation support Virtual shares

Language classes Tax incentive, subject to eligibility

📌 Formal Verification Lead (Cataluña)
🏢 Hireroo
📍 Cataluña