STA & Synthesis Lead Engineer (Barcelona)

STA & Synthesis Lead Engineer (Barcelona)

04 oct
|
Hireroo
|
Barcelona

04 oct

Hireroo

Barcelona

Job Description
Our partner is expanding its semiconductor engineering team and is looking for an experienced STA & Synthesis Lead Engineer to own synthesis, static timing analysis, timing closure and design optimization across complex digital designs.
You will work from RTL through implementation and sign off, driving synthesis quality, PPA optimization and timing convergence across hierarchical and top level designs. The role requires close collaboration with RTL, DFT and Physical Design teams to identify bottlenecks, resolve implementation issues and ensure robust timing closure.
Level: SeniorLocation: Barcelona, Spain, Hybrid
Responsibilities

Drive physical aware RTL to gate synthesis at block and top level
Optimize designs for power, performance and area
Analyze synthesis results and identify optimization opportunities
Develop, validate and debug SDC constraints
Define clocks, generated clocks, I/O constraints and timing exceptions
Manage false paths, multicycle paths and case analysis
Perform MMMC static timing analysis and timing sign off
Analyze setup, hold, recovery,



removal and clock gating checks
Investigate critical paths and timing bottlenecks
Generate, implement and validate timing and functional ECOs
Resolve post placement and post route timing issues
Support functional, scan and DFT timing modes
Work with RTL, DFT and Physical Design teams to improve design convergence
Improve synthesis and timing closure methodology

Requirements

7+ years of hands on synthesis and STA experience
Strong logic and physical synthesis experience
PPA optimization across complex digital designs
Deep knowledge of STA and MMMC analysis
Strong SDC development, validation and debugging
Timing closure across block, subsystem and top level designs
ECO implementation and validation
Strong knowledge of setup, hold and clock related timing analysis
Understanding of clock skew, latency, jitter, uncertainty and variation
Knowledge of PVT conditions and their impact on timing
Exper

📌 STA & Synthesis Lead Engineer (Barcelona)
🏢 Hireroo
📍 Barcelona

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