Job Description
Our partner is looking for a Senior DDR Design Engineer to design, develop and integrate high performance memory subsystem solutions for advanced semiconductor products.
You will work closely with architecture, RTL, verification and implementation teams on memory controller design, interface integration, timing and validation. The role requires strong ownership of memory subsystem development and the ability to support designs from architecture through implementation and tape out.
Location: Barcelona, Spain, HybridLevel: Senior
Responsibilities

Design and integrate DDR or HBM memory subsystems
Develop and integrate memory controllers within SoC environments
Implement and review RTL using Verilog or VHDL
Work with AXI based interfaces and system integration
Translate architecture requirements into robust memory subsystem designs
Apply timing constraints and support timing analysis and closure
Perform block level testing and validation
Debug memory subsystem and interface issues
Collaborate with architecture, RTL and verification teams




Support integration through implementation and tape out
Contribute to design reviews and technical decisions

Requirements

8+ years of relevant industry experience
Strong DDR or HBM memory experience
Proven memory controller design or integration experience
Strong knowledge of AXI protocol
RTL design using Verilog or VHDL
Experience with timing and timing constraints
Block level testing and validation
Understanding of SoC memory subsystem integration
Strong debugging and problem solving skills
Ability to work across architecture, RTL and verification teams

Optional / Desired

RISC V architecture experience
Master or PhD
Python, Perl, Bash or Tcl
Git or SVN
Participation in 2 successful tape outs
Experience with complex SoC memory subsystems
Experience supporting timing closure and integration
Broader knowledge of memory architecture and system performance

What’s in it for you?

Versátil working hours
Hybrid model, 4

📌 DDR Design Engineer (Barcelona)
🏢 Hireroo
📍 Barcelona