04 oct
|
Semidynamics
|
Barcelona
04 oct
Semidynamics
Barcelona
Semidynamics seeks a Design Verification Engineer to lead subsystem and IP‑level verification for high‑speed interfaces in AI chips. You will guide a team of verification engineers, coordinating with RTL, SoC architecture, firmware, and other DV teams to deliver sign‑off quality designs.The role requires hands‑on leadership, deep technical expertise, and cross‑functional collaboration in a hybrid setup with four days in Barcelona and one day WFH.#J-18808-Ljbffr
📌 Hybrid: Lead Design Verification Engineer For Ai Chip Socs (Barcelona)
🏢 Semidynamics
📍 Barcelona