Senior Verification Engineer, LSU and Data Cache (Barcelona)

Senior Verification Engineer, LSU and Data Cache (Barcelona)

04 oct
|
Hireroo
|
Barcelona

04 oct

Hireroo

Barcelona

Job Description

Obtenga más información sobre las tareas generales relacionadas con esta posibilidad a continuación, así como sobre las habilidades requeridas.
Our partner is looking for a Senior Verification Engineer to own verification of the Load/Store Unit, data cache and related bus interfaces within a processor core.

The role covers memory ordering, cache and TLB interaction, address generation, forwarding, speculative execution, vector accesses, exceptions and pipeline hazards. You will own the verification scope from planning through sign off, working closely with architecture, RTL and other verification teams.

Location: Barcelona, Spain, Hybrid
Level: Senior

Responsibilities

-
- Own the LSU verification plan, test strategy and closure criteria
- Build and extend UVM testbench components, including drivers, monitors, scoreboards and memory models
- Develop directed and constrained random tests
- Verify store to load forwarding and memory ordering
- Verify speculative loads and vector memory accesses
- Cover misaligned and split accesses, exceptions and faults




- Verify cache, TLB and load/store pipeline interactions
- Drive functional and code coverage closure
- Manage regressions and analyze verification results
- Apply formal verification to ordering or coherency properties where required
- Debug RTL and testbench failures and drive root cause analysis
- Resolve cross unit verification issues with architecture and design teams
- Review verification code and mentor junior engineers

Requirements

-
- 5+ years of ASIC functional verification experience
- Strong SystemVerilog and UVM
- Hands on testbench architecture experience
- Deep understanding of LSU, caches, TLBs and memory subsystems
- Strong knowledge of memory consistency and load/store pipelines
- RISC V ISA and privileged specification
- AXI4, AXI5 Lite and CHI
- Coverage driven verification
- Functional and code coverage closure
- Regression management
- Strong RTL debugging skills
- Verdi, DV

📌 Senior Verification Engineer, LSU and Data Cache (Barcelona)
🏢 Hireroo
📍 Barcelona

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