03 oct
|
Jobrapido
|
España
In this role you will contribute to receiver technology projects, focusing on migrating an architecture from Xilinx MPSoC/FPGA to an ASIC solution. Hybrid working model
~Intensive Fridays and summer hours
~ language learning support in-house training
Develop and adapt RTL blocks (VHDL/Verilog/SystemVerilog)
Participate in functional verification, simulation, and design debugging
Contribute to the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT, and design closure
digital RTL design knowledge
embedded ARM/RISC-V and hardware/software partitioning
VHDL
RTL design
📌 Technology Design Engineer (España)
🏢 Jobrapido
📍 España