Remoto: Trabajo híbrido

SelectLevelID: HSIP-1DescriptionWe are seeking a Design Verification Engineer to lead subsystem and IP‑level functional verification of high‑speed interface protocol blocks in our AI chips. You will guide a team of highly skilled verification engineers to deliver sign‑off‑quality designs, collaborating closely with RTL design, SoC architecture, firmware, and other verification teams. This is a hands‑on leadership role requiring deep technical expertise and cross‑functional coordination.Key ResponsibilitiesArchitect, set up, and debug functional verification environments across multiple design blocks and subsystem levels.Serve as the protocol expert, providing clarity on expected behaviors of AMBA and high‑speed interfaces (PCIe, UCIe, SerDes, etc.).Debug mismatches between RTL, DV models, and specifications, ensuring functional correctness and compliance.Develop and maintain UVM‑based testbenches, scripts, and flows to automate verification compile/run cycles.Triage and root‑cause simulation failures, track bugs, and drive closure with cross‑functional teams.Optimize simulation runtime, capacity, and compile turnaround for large‑scale designs.Maintain detailed documentation of methodologies, flows, and known issues.Why SemidynamicsJoin one of Europe’s most promising deep‑tech semiconductor startups,



building AI chips from silicon to systems.Accelerated career growth and technical ownership.Hybrid work model: 4 days in the Barcelona office (city center), 1 day WFH, plus 1 week of “work from anywhere.”Competitive compensation and benefits.A collaborative, technically driven environment that values clarity, ownership, and innovation.RequirementsBachelor’s or Master’s degree in Electrical or Computer Engineering (or related field).10+ years of experience in ASIC/SoC design verification, with recent focus on high‑speed protocols (PCIe, UCIe, SerDes).Deep expertise in on‑chip bus protocols (AXI, CXS, AHB, CHI, etc.).Proven experience developing UVM‑based testbenches and driving coverage‑driven sign‑off flows.Strong understanding of digital design fundamentals and SoC microarchitectures.Proficiency in Verilog/SystemVerilog and simulation tools (VCS, Xcelium, Questa).Exceptional debugging and problem‑solving skills, with the ability to work independently on complex challenges.Preferred QualificationsExperience using AI‑assisted tools for design verification and regression analysis.Familiarity with version control systems (Git, Perforce) and job scheduling frameworks (LSF, Grid Engine).Strong scripting skills in Perl, Python, or TCL for automation and debug workflows.Excellent communication and documentation skills.#J-18808-Ljbffr

📌 Lead Design Verification Engineer – High‑Speed Interface Protocols (Madrid)
🏢 Semidynamics
📍 Madrid