Job Description Our partner is looking for a Senior
Verification Engineer to own verification of the Load/Store Unit,
data cache and related bus interfaces within a processor core. The
role covers memory ordering, cache and TLB interaction, address
generation, forwarding, speculative execution, vector accesses,
exceptions and pipeline hazards. You will own the verification
scope from planning through sign off, working closely with
architecture, RTL and other verification teams. Location:
Barcelona, Spain, Hybrid Level: Senior Responsibilities Own the LSU
verification plan, test strategy and closure criteria Build and
extend UVM testbench components, including drivers, monitors,
scoreboards and memory models Develop directed and constrained
random tests Verify store to load forwarding and memory ordering
Verify speculative loads and vector memory accesses Cover
misaligned and split accesses, exceptions and faults Verify cache,
TLB and load/store pipeline interactions Drive functional and code
coverage closure Manage regressions and analyze verification
results Apply formal verification to ordering or coherency
properties where required Debug RTL and testbench failures and
drive root cause analysis Resolve cross unit verification issues
with architecture and design teams Review verification code and




mentor junior engineers Requirements 5+ years of ASIC functional
verification experience Strong SystemVerilog and UVM Hands on
testbench architecture experience Deep understanding of LSU,
caches, TLBs and memory subsystems Strong knowledge of memory
consistency and load/store pipelines RISC V ISA and privileged
specification AXI4, AXI5 Lite and CHI Coverage driven verification
Functional and code coverage closure Regression management Strong
RTL debugging skills Verdi, DVE or similar waveform tools BS or MS
in Electrical Engineering, Computer Engineering, Computer Science
or related field Optional / Desired Formal verification using
JasperGold or similar CPU architecture and memory execution
pipeline experience Prior LSU, cache or memory controller
verification RISC V, ARM or x86 memory models Python or Perl
scripting Technical mentoring experience Veloce or ZeBu AFL++ or
other fuzzing techniques SystemC or C++ testbenches What’s in it
for you? Versátil working hours Hybrid model, 4 days office, 1 day
from home 1 week per year working from anywhere 25 days annual
leave plus December 24 and 31 Monthly food allowance Private
medical insurance Relocation bonus Housing search support Visa
support if required Family relocation support Virtual shares
Language classes Tax incentive, subject to
eligibility

📌 Senior Verification Engineer, LSU and Data Cache (Cataluña)
🏢 Hireroo
📍 Cataluña