Semidynamics is seeking a static formal verification lead to ensure functional correctness and low-power intent across the design lifecycle. You will drive RTL-to-Gate and Gate-to-Gate equivalence checks, debug LEC failures, and guarantee convergence across synthesis, place-and-route, and ECO cycles.
You will collaborate with RTL, Synthesis, DFT, and Physical Design teams to resolve design mismatches, perform ECO validation, and develop automation for LEC sign-off.
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📌 Senior Formal Verification Lead (Cataluña)
🏢 Semidynamics
📍 Cataluña
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