Experteer Overview

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As Principal Physical Design Engineer, you lead end-to-end physical implementation and signoff of complex SoCs across advanced nodes. You combine RTL-to-GDSII hands-on work with design convergence and team leadership to deliver high-quality silicon in partnership with PD, DFT, Verification, CAD, and signoff teams. You drive timing closure, optimize PPA, and guide a geographically distributed PD team to meet critical milestones. This role offers impact in a high-performance, cross-functional environment on flagship projects.

Compensaciones / Beneficios
• Own RTL-to-GDSII implementation, including floorplanning, CTS, routing, EC/verification, ECOs, and STA closure
• Review timing constraints and closure results, guiding PD and Design teams
• Hands-on with Cadence and/or Synopsys PD flows to drive implementation,



optimization, debugging, and signoff
• Lead setup/hold timing, IR/EM, congestion resolution, and physical verification to meet PPA targets
• Lead signoff activities including multi-mode/multi-corner STA, DRC/LVS, and power analysis
• Provide leadership for a distributed PD team, coordinating planning, execution, and risk mitigation across locations
• Drive project risk management, communicating trade-offs and status to stakeholders and leadership

Responsabilidades
• 10+ years of physical design experience with successful tape-outs on advanced technology nodes
• Hands-on experience with industry-standard physical design and signoff tools
• B.Tech. xghoner , M.Tech., or higher in Electrical or Electronics Engineering (or equivalent)

Requisitos principales
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📌 Principal Physical Design Engineer (Castellón de la Plana)
🏢 Analog Devices
📍 Castellón de la Plana