Overview
In this role, you will contribute to the end-to-end physical design of complex projects and RISC-V IP from a Barcelona-based team. You will work on high-impact PD tasks that shape silicon performance and area, collaborating with cross-functional engineers to meet project milestones. You’ll tackle challenges across the PD flow, from netlist to GDS, enabling scalable growth as the company expands. This is a chance to grow with a fast-moving team and take on increasing responsibilities in a thriving semiconductor environment.
Responsabilidades
Execute the PD flow from netlist to GDS (floorplanning, power planning, placement & optimisation, CTS, routing, post-route optimisation, DRC closure)
Collaborate on high-complexity PD tasks for RISC-V IP
Support design closure and performance goals across projects
Requisitos principales
Bachelor in Electronics or related field
Knowledge of the entire PD flow from netlist to GDS
Experience in logic synthesis, Conformal, static timing analysis and Place and Route (PnR)
PD flow knowledge (netlist to GDS)
Floorplanning
Power planning
Placement & Optimisation
CTS
Routing

📌 Design Engineer (Barcelona)
🏢 Jobrapido
📍 Barcelona