Senior Hardware Design Engineer (FPGA) | Job Details
we'll tell you what's not on the web. You will join the receiving team to lead FPGA/SoC based hardware design projects, architecture definition, junior team mentoring and critical system optimization.
Coding in VHDL/Verilog
Mentoring of junior engineers
For this position, we are looking for hardware engineering experts with experience in FPGA development, advanced VHDL/Verilog, synthesis and verification tools (Vivado, Quartus, ModelSim, QuestaSim), modular/IP design, timing optimization, high speed interfaces, C++ or Rust, Python, GIT. Knowledge of Process Automation, signal processing, HDL coder, soft core processors, standards (DO-254, ECSS), ASIC design would be an asset.
We will also value availability to travel because, although the bulk of the work is done in GMV's facilities in Madrid,



travel for meetings or tests in European countries is necessary.
Hybrid working model and 8 weeks per year of teleworking outside your usual geographical area. Adaptable start and finish times, and intensive working hours Fridays and in summer. Personalized career plan development, training and language learning support. We can offer you a relocation package.
Competitive compensation with ongoing reviews, flexible compensation and discount on brands. Health, dental and accident insurance; free fruit and coffee, physical, mental and financial health training, and much more
In our recruitment processes you will always have telephone and personal contact, face-to-face or online, with our talent acquisition team. JOIN US#LI-Hybrid

📌 Senior Hardware Design Engineer (Tres Cantos)
🏢 GMV
📍 Tres Cantos