GMV is seeking an experienced hardware engineer to contribute to receiver technology projects. You will migrate architectures from Xilinx MPSoC/FPGA to ASIC, shaping the target architecture, implementing RTL blocks, and optimizing interfaces while supporting verification and the overall ASIC flow.
In this hands-on role, you will work within the GMV Receivers team on R&D-driven; efforts to deliver new ASIC-based capabilities.
📌 ASIC Design Engineer – RTL Architecture (Madrid)
🏢 GMV
📍 Madrid