Role OverviewAs a low power verification lead, you will play a key role in ensuring low-power intent integrity across the design lifecycle. You will be responsible for VCLP signoff, ensuring seamless convergence between RTL, synthesis, and physical design stages for hierarchical designs.Key ResponsibilitiesUnderstand low power specs and write UPF for hierarchical designsValidate low-power architecture, UPF constraints, and intent across multiple domains.Debug VCLP failures, including issues arising from clock gating, retention, isolation, and level shiftersEnsure convergence of UPF across synthesis, place-and-route, and ECO cyclesWork closely with RTL, Synthesis, DFT,



and Physical Design teams to resolve low power issuesDevelop automation scripts and improve methodology for VCLP sign-offTechnical SkillsBachelor’s or Master’s degree in Electrical/Electronics Engineering or related discipline7+ years of experience in low power methodologies and low power static verification using VCLPStrong understanding of low-power design concepts (UPF) and methodologiesExperience with synthesis, netlist optimizations, and equivalence debuggingProficiency in scripting languages such as TCL, Python, or PerlExperience with hierarchical Sub system level VCLP flowsPreferred QualificationsFamiliarity with DFT concepts and scan impact on UPF and UPF checksKnowledge of STA and Physical Design interactions impacting UPFSuccess in This Role Looks LikeClean VCLP sign-offFast turnaround time in debugging and resolving VCLP/UPF issuesRobust, scalable VCLP methodologies across projectsStrong cross-team collaboration ensuring smooth design convergence

📌 Low Power Verification Lead (Cataluña)
🏢 Semidynamics
📍 Cataluña