The TMRW Foundation SILICON in Barcelona, Spain, seeks a mid-senior Digital IC Designer to drive RTL design, verification, and implementation for cutting-edge IC projects. You will employ Cadence tools to meet performance, power, and area targets across complex digital blocks.
Responsibilities include RTL coding in Verilog/VHDL, functional verification, and timing sign-off using Tempus, Genus, Innovus and NCLaunch/Incisive.
📌 Digital IC Designer: RTL, Cadence Expert, Timing (España)
🏢 TMRW
📍 España