Job Description
Our partner is expanding its semiconductor engineering team and is looking for an experienced STA & Synthesis Lead Engineer to own synthesis, static timing analysis, timing closure and design optimization across complex digital designs.
You will work across RTL through implementation, driving timing sign off and PPA optimization while collaborating closely with RTL, DFT and Physical Design teams.
Level: Senior
Location: Barcelona, Spain, Hybrid
Responsibilities
• Drive physical aware RTL to gate synthesis at block and top level
• Optimize designs for power, performance and area
• Perform MMMC static timing analysis and timing sign off
• Analyze setup, hold, recovery, removal and clock gating checks
• Identify timing bottlenecks and drive timing closure
• Generate and validate timing and functional ECOs
• Resolve timing issues after placement and routing
• Support DFT and scan timing modes
• Work with RTL,
DFT and Physical Design teams to improve design convergence
Requirements
• 7+ years of synthesis and STA experience
• Logic synthesis and PPA optimization
• Strong STA and MMMC expertise
• SDC development and debugging
• Timing closure and ECO implementation
• PrimeTime, Fusion Compiler, Formality and VCLP
• Advanced semiconductor node experience, ideally 3nm or below
• Hierarchical and top level STA
• Strong understanding of clocks, timing variation and PVT
• Experience with physical synthesis and timing sign off
• Strong debugging and problem solving skills
Valued: DFT and scan timing, CTS timing, hierarchical implementation and advanced node designs.
What’s in it for you?
Our partner offers an opportunity to work on advanced semiconductor development in Barcelona, with significant ownership of synthesis and timing methodology.
• 4 days per week in the Barcelona office, 1 day from home
• Flexibl
📌 STA & Synthesis Lead Engineer (Barcelona)
🏢 Hireroo
📍 Barcelona
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