ASIC Design Engineer - RTL/Verilog, Hybrid, MPSoC (Tres Cantos)

ASIC Design Engineer - RTL/Verilog, Hybrid, MPSoC (Tres Cantos)

28 sep
|
GMV
|
Tres Cantos

28 sep

GMV

Tres Cantos

GMV is expanding its GNSS-User Segment Navigation unit in Madrid to work on ASIC migration from Xilinx MPSoC/FPGA to ASIC solutions. You will define target architecture, develop RTL blocks, and participate in functional verification and design closure.

Joining the Receivers team offers hybrid work, international mobility, relocation support, and a strong emphasis on R&D; and patentable designs, with competitive compensation and career development.

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📌 ASIC Design Engineer - RTL/Verilog, Hybrid, MPSoC (Tres Cantos)
🏢 GMV
📍 Tres Cantos

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