Semidynamics is seeking a seasoned Low Power Verification Lead to ensure UPF integrity across RTL, synthesis, and physical design for hierarchical blocks.
Se pueden requerir diversas habilidades interpersonales y experiencia para el siguiente puesto. Por favor, asegúrese de consultar la descripción a continuación con atención.
You will own VCLP sign-off and drive convergence of low-power intent throughout the design flow. xhfqzwm
Collaborating with RTL, Synthesis, DFT and PD teams, you will develop automation, debug VCLP issues, and strengthen methodologies to deliver robust, scalable VCLP sign-off across projects.