26 sep
|
Semidynamics
|
Gerona
26 sep
Semidynamics
Gerona
Semidynamics is seeking a seasoned Low Power Verification Lead to ensure UPF integrity across RTL, synthesis, and physical design for hierarchical blocks. You will own VCLP sign-off and drive convergence of low-power intent throughout the design flow.Collaborating with RTL, Synthesis, DFT and PD teams, you will develop automation, debug VCLP issues, and strengthen methodologies to deliver robust, scalable VCLP sign-off across projects.#J-18808-Ljbffr
📌 Low-Power Verification Lead: Vclp & Upf Convergence (Gerona)
🏢 Semidynamics
📍 Gerona