Overview Senior Verification Engineer for a Barcelona-based semiconductor startup building high-performance RISC-V CPUs. You will contribute to verification in a modern UVM-based environment, guiding strategy and owning verification across tape-outs. Collaboration with architecture and design teams is key to shipping silicon. The role offers relocation and visa sponsorship, and exposure to fast-moving development in AI/ML-focused cores.





Compensaciones / Beneficiosrelocation packagevisa sponsorshipSpanish lessons on onboarding ResponsabilidadesVerify complex digital designs in a UVM-based environment using SystemVerilogInfluence verification strategy and methodologiesOwn verification progress across multiple tape-outsCollaborate closely with architecture and design teamsHandle cross-functional verification tasks in a startup settingContribute to verification coverage, metrics, and debuggingSupport high-speed protocols and coherent system verification when relevant Requisitos principalesStrong experience with UVM, SystemVerilogScripting skills (Python, Perl, Bash, or TCL)Version control knowledge (Git or SVN)Exposure to formal verification is a plusExperience with coherent systems, CHI protocol, cache architectures, PCIe or related high-speed protocols is valuableCross-functional collaborationOwnership and initiativeAdaptability in a fast-moving startupUVMSystemVerilogPython

📌 Senior Verification Engineer (Barcelona)
🏢 Jobrapido
📍 Barcelona