OverviewDescubra si esta oportunidad es adecuada para usted leyendo toda la información que sigue a continuación.In this role you will drive end-to-end physical implementation and signoff of digital blocks and SoCs, collaborating across a distributed team. You will apply practical RTL-to-GDSII expertise to deliver high-quality results and deepen your knowledge of physical design flows. You’ll tackle timing, power, and layout challenges, guiding the design team toward robust implementations. This position offers exposure to Cadence or Synopsys-driven signoff work and a chance to contribute to advanced technologies at a integral leader.ResponsabilidadesExecute RTL-to-GDSII implementation activities (floor-planning, CTS, routing, EC, timing closure, physical verification)Leverage Cadence or Synopsys-based flows to support implementation, optimization,



and signoffReview results against synthesis and timing constraints and provide design feedbackAnalyse and resolve timing, power, IR/EM, DRC, LVS issues with guidance from senior engineersDemonstrate strong communication and teamwork, taking ownership of implementation tasksRequisitos principalesB.Tech. xhfqzwm, M.Tech., or equivalent qualification in Electrical Engineering, Electronics Engineering, or related disciplineApproximately 3–7 years of relevant physical design or digital implementation experienceHands-on experience with industry-standard physical design and signoff tools, preferably Cadence or Synopsys environmentStrong communicationTeamworkWillingness to learnRTL-to-GDSII flow understandingFloor-planning, CTS, routingTiming closure and signoff

📌 Principal Physical Design Engineer (Sabiñánigo)
🏢 Analog Devices
📍 Sabiñánigo