In this role you will lead FPGA/SoC hardware design projects within GMV’s space sector, driving architecture definition and system optimization. You will work closely with a cross-functional team, mentoring junior engineers and shaping critical hardware solutions. Expect hands-on work with architecture, HDL coding, and advanced verification to meet stringent performance and reliability needs. You will collaborate across locations, contributing to system-level optimization and documentation. This is an opportunity to influence high-impact space hardware and grow as a technical leader. 8 weeks teleworking per year Versátil start/finish times Career plan development,
training and language learning support National and international mobility Relocation package Define architecture for FPGA/SoC hardware Code in VHDL/Verilog Perform advanced verification using SystemVerilog/UVM Optimize resources and timing Define HW/SW interfaces Produce technical documentation Advanced VHDL/Verilog, synthesis and verification tools (Vivado, Quartus, ModelSim, QuestaSim) Modular/IP design, timing optimization, high-speed interfaces C++ or Rust, Python, Git Knowledge of Process Automation, signal processing, HDL coder, soft core processors, DO-254, ECSS ASIC design would be an asset Willingness to travel within Europe mentoring and coaching team collaboration effective communication VHDL SystemVerilog/UVM Senior Hardware Design Engineer (FPGA) tres cantos, madrid, es