In this role you will contribute to receiver technology projects, focusing on migrating an architecture from Xilinx MPSoC/FPGA to an ASIC solution. You will shape the target ASIC architecture, implement RTL blocks, and optimize internal interfaces while supporting verification and the overall ASIC flow. You’ll work within the GMV Receivers team on R&D-driven efforts that aim to deliver new ASIC-based capabilities. This is a hands-on, impact-oriented opportunity at the intersection of hardware architecture and RTL development.8 weeks per year teleworkingFlexible start/finish timesIntensive Fridays and summer hourslanguage learning support in-house trainingDefine and evolve the target ASIC architectureDevelop and adapt RTL blocks (VHDL/Verilog/SystemVerilog)Analyze and optimize internal interfaces (buses, memories, synchronization, clocks,



resets)Participate in functional verification, simulation, and design debuggingContribute to the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT, and design closureDocument architecture, decisions, and validation resultsdigital RTL design knowledgeFPGA, SoC or MPSoC architectures understandinginternal buses, IP integration, and functional verification experienceASIC flow experience including simulation and synthesis toolsSystemVerilog, UVM, assertions or cocotb (verification)embedded ARM/RISC-V and hardware/software partitioningexperience with Synopsys, Cadence, Siemens EDA, Vivado, or Vitis toolsVHDLFPGA#J-18808-Ljbffr

📌 Asic Design Engineer - Tres Cantos (Madrid)
🏢 GMV
📍 Madrid