Overview

In this role you will drive end-to-end physical implementation and signoff of digital blocks and SoCs, collaborating across a distributed team. You will apply practical RTL-to-GDSII expertise to deliver high-quality results and deepen your knowledge of physical design flows. You’ll tackle timing, power, and layout challenges, guiding the design team toward robust implementations. This position offers exposure to Cadence or Synopsys-driven signoff work and a chance to contribute to advanced technologies at a integral leader.

Responsabilidades

- Execute RTL-to-GDSII implementation activities (floor-planning, CTS, routing, EC, timing closure, physical verification)
- Leverage Cadence or Synopsys-based flows to support implementation, optimization, and signoff
- Review results against synthesis and timing constraints and provide design feedback
- Analyse and resolve timing, power,



IR/EM, DRC, LVS issues with guidance from senior engineers
- Demonstrate strong communication and teamwork, taking ownership of implementation tasks

Requisitos principales

- B.Tech., M.Tech., or equivalent qualification in Electrical Engineering, Electronics Engineering, or related discipline
- Approximately 3–7 years of relevant physical design or digital implementation experience
- Hands-on experience with industry-standard physical design and signoff tools, preferably Cadence or Synopsys environment

- Strong communication
- Teamwork
- Willingness to learn
- RTL-to-GDSII flow understanding
- Floor-planning, CTS, routing
- Timing closure and signoff

📌 Senior Physical Design Engineer - Analog Devices (Comunidad Valenciana)
🏢 Analog Devices
📍 Comunidad Valenciana