In this role you will deliver digital subsystems and high-precision analog blocks for next‑gen consumer products. You’ll work within a cross‑functional CSS team focused on capacitive sensing and optical sensing, shaping devices used in portable electronics. You’ll apply state‑of‑the‑art physical design methods to enable scalable, tape‑out ready designs and collaborate across geographies to meet schedule milestones. This is a growth‑oriented position at a general leader driving intelligent edge solutions.Floorplan development including power/ground and clock distributionLogic synthesis, cell placement, and interconnect routingEquivalence-checking, timing closure, and physical verification (LVS,



DRC)Collaborate with RTL designers to resolve challenging problemsOwn and deliver digital subsystems of significant size and complexityDevelop schedules and monitor progressCoordinate effective teamwork across geographically dispersed locationsB.Tech/M.Tech in EE/ECE with 10+ years of digital implementation experienceStrong knowledge of floor planning, place and route, CTS, STA, ECO methodology, power analysis, and physical design verificationBroad experience in synthesis and timing constraintsExperience with 40nm digital implementationScripting skills in Tcl, SKILL, and PerlCadence tool experience preferredExperience with Perforce/Methodics for versioningKnowledge of CPF/UPF methodology (advantage)Cadence Virtuoso knowledge (advantage)Tape-out ready GDS2 database experience (advantage)Technical ownership and hands-on implementation capabilityStrong interpersonal, teamwork and communication skillsteamworkcommunicationownershipfloorplanningplace and route#J-18808-Ljbffr

📌 Staff Engineer, Physical Design - València (Valencia)
🏢 Analog Devices
📍 Valencia