Job Description Our client is expanding their Verification organization and is looking for Mid, Senior and Lead Verification Engineers with strong expertise in RTL verification, processor architecture, SoC verification and advanced interface verification.

Our client is expanding their Verification organization and is looking for Mid, Senior and Lead Verification Engineers with strong expertise in RTL verification, processor architecture, SoC verification and advanced interface verification. In this role, you will verify complex digital designs at RTL level according to architecture specifications. You will build and maintain verification environments, manage regressions, debug simulation results and contribute to verification closure for high performance processor designs. The current priority focus areas include processor verification, memory and coherency verification, PCIe, UCIe, LPDDR, PCS, FEC, SERDES, SoC Top, clock, reset, boot, interrupts, power, SDC and constraints.

Location: Barcelona, Spain - Hybrid

Employment Type: Full time

Responsibilities As a Mid / Senior / Lead Verification Engineer, your broad responsibilities will include but are not limited to:

Mid / Senior Verification Engineer

Verify complex RTL designs according to architecture specifications

Develop and maintain verification environments using SystemVerilog and UVM

Manage simulation and regression environments

Perform block, subsystem and top level verification

Apply formal and dynamic verification methods

Analyze and debug simulation results

Develop tests, checkers and coverage models

Contribute to verification planning, coverage analysis and closure

Work closely with architecture and RTL design teams

Verify processor, SoC or interface features based on the assigned specialty

Additional Responsibilities For Lead Verification Engineer

Lead verification activities for assigned blocks or subsystems

Define verification strategy and methodology

Coordinate planning, milestones and closure





Mentor verification engineers

Act as the main escalation point for complex verification issues

Drive verification quality across projects

Coordinate verification work across RTL, architecture and physical design teams

Requirements Mid Verification Engineer

Around 4 plus years of relevant experience

Experience with RTL or FPGA verification

Strong knowledge of SystemVerilog and UVM

Experience with simulation, regression and debugging

Knowledge of scripting languages, Python, Perl, Bash or Tcl

Knowledge of Git or SVN

Strong problem solving skills

English level C1

Bachelor, Master or PhD in Electronics, Computer Engineering or related field

Senior Verification Engineer

Around 8 plus years of relevant industrial experience

Strong experience in block, subsystem or top level verification

Experience with formal and dynamic verification methods

Strong verification planning and coverage closure experience

Ability to debug complex processor, SoC or protocol issues

Strong communication with RTL and architecture teams

Lead Verification Engineer

Proven experience leading verification work or teams

Ability to define verification strategy and methodology

Experience coordinating verification milestones and closure

Strong ownership of technical decisions and delivery

Ability to mentor engineers and guide complex debug

Experience coordinating verification work across multiple teams or technical domains

Preferred / Valued Knowledge Experience working with RISC V architecture is highly valued, especially within processor, SoC, RTL, verification, firmware,



software, PCIe, DDR, PCS, DFT, Physical Design or hardware environments.

Priority focus areas

Core processor verification, branch prediction, out of order execution, renamer, dispatch

Memory and coherency verification, memory model, memory consistency, ordering, virtual memory, CHI

Interface verification, PCIe, UCIe, LPDDR, PCS, FEC, SERDES

SoC Top verification, boot, power, clock, reset, interrupts, SDC and constraints

What’s in it for you? Our client offers an exciting, challenging role in a collaborative, dynamic environment. The right person will find many career growth opportunities in their company, whether you want to advance your technical skills or aspire to leadership in the future.

Benefits

Flexible working hours (office open between 7 AM and 9 PM, employees manage their own schedule)

Hybrid working model

One week per year work from anywhere

25 days annual leave plus December 24 and 31

€150 per month food allowance (≈ €1800 per year additional compensation)

Private medical insurance

One time relocation bonus paid with the first salary

Support with housing search through an agency

Visa support if required

Relocation support for family

Virtual shares

Language classes (Spanish, English, Catalan)

Tax incentive

We redefine recruitment by focusing on a rich back to basics approach that focuses on genuine relationship building both with our clients and our candidates, offering a truly bespoke service that revolves around that perfect match. With general reach and equipped with profound industry insights and an extensive network, we have now earned the trust of globally recognized iGaming and fintech companies. Standing firmly as the go-to partner for these industry leaders, collaborating on numerous local and global HR projects, we take pride in our role as true lifetime partners for both our clients and candidates.

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📌 Verification Engineer - PCIe / UCIe / LPDDR / PCS / SERDES / SoC Top (Mid / Senior / Lead) (Madrid)
🏢 Hireroo
📍 Madrid