As a Senior Memory Design Engineer, you will play a crucial role in designing and developing memory subsystem solutions for our semiconductor portfolio. You will work within the Memory Design Team, collaborating closely with other highly skilled engineering teams to create efficient, high-performance memory subsystems that are essential for modern designs.
Why Seynamics? Work at one of Europe’s most promising deep-tech semiconductor start up - from silicon to systems - Se
- ynamics.
- Accelerated development path.
- 4 days per week in the Barcelona office (city center), 1 day WFH.
- 1 week of work from everywhere in the world.
- Competitive package.
- A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.
Requirements
- 8+ years of industry experience
- Knowledge of DDR or HBM memories, with proven experience in the design and/or integration of memory controllers
- Experience with the AXI protocol
- Proficiency in RTL design using Verilog or VHDL
- Experience with timing and timing constraints
- Experience with basic block-level testing
Preferred Qualifications
- Master's or PhD degree
- Knowledge of scripting languages (Python, Perl, Bash, TCL)
- Knowledge of revision control methodologies and tools (Git, SVN)
- Having participated to two succesful tapeouts
SENIOR
📌 DDR Design Engineer (España)
🏢 Semidynamics
📍 España
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