Overview
¿Es usted el solicitante adecuado para esta posibilidad? Descúbralo leyendo el resumen del puesto a continuación.
Senior Verification Engineer for a Barcelona-based semiconductor startup building high-performance RISC-V CPUs. You will contribute to verification in a modern UVM-based environment, guiding strategy and owning verification across tape-outs. Collaboration with architecture and design teams is key to shipping silicon. The role offers relocation and visa sponsorship, and exposure to fast-moving development in AI/ML-focused cores.
Compensaciones / Beneficios
relocation package
visa sponsorship
Spanish lessons on onboarding
Responsabilidades
Verify complex digital designs in a UVM-based environment using SystemVerilog
Influence verification strategy and methodologies
Own verification progress across multiple tape-outs




Collaborate closely with architecture and design teams
Handle cross-functional verification tasks in a startup setting
Contribute to verification coverage, metrics, and debugging
Support high-speed protocols and coherent system verification when relevant
Requisitos principales
Strong experience with UVM, SystemVerilog
Scripting skills xqbhyrx (Python, Perl, Bash, or TCL)
Version control knowledge (Git or SVN)
Exposure to formal verification is a plus
Experience with coherent systems, CHI protocol, cache architectures, PCIe or related high-speed protocols is valuable
Cross-functional collaboration
Ownership and initiative
Adaptability in a fast-moving startup
UVM
SystemVerilog
Python

📌 Senior Verification Engineer (Barcelona)
🏢 Intellectual Capital Resources
📍 Barcelona