Overview In this role you will lead FPGA-based prototyping and model development with self-checking mechanisms, enabling robust HW/SW co-design. You will architect digital blocks and manage RTL design to meet timing, area, and power targets, collaborating with verification and analog teams. You will drive the flow to convert RTL to silicon with the implementation team and define timing constraints with static timing analysis.

You will work with architecture to determine functionality protocols and engage with customers and stakeholders to ensure design targets align with product goals. This position offers impact across a mixed-signal SOC environment and opportunities to shape digital design at scale

Responsabilidades FPGA prototyping of design

Development of models and self-checking mechanisms for FPGA

HW & SW codesign

Architectural design and specification of blocks

Verilog/SystemVerilog RTL design

Design to meet timing, area, low-power, DFT, manufacturing test and timing targets

Interaction with verification and analog teams

Interaction with implementation team to convert RTL to silicon





Define timing constraints and perform static timing analysis

Work with architecture and design teams to determine functionality protocols

Requisitos principales Bachelors degree in Electronic Engineering

Architectural design and specification of complex systems (SOC with processors)

Deep knowledge of FPGA development flow

FPGA modelling

Verilog/SystemVerilog RTL design with emphasis on AHB, AXI, and ARM cores

Design to meet timing, area, low-power, manufacturing test and timing targets

Interaction with verification and analog teams

Interaction with implementation team to convert RTL to silicon

Strong interpersonal, teamwork and communication skills

Precise documentation and attention to detail

Quick to adopt new technologies

Self-motivated and enthusiastic

Strong interpersonal skills

Teamwork

Clear communication

FPGA development flow

FPGA modelling

Verilog/SystemVerilog RTL design (AHB, AXI, ARM cores)

📌 Senior Engineer, Digital Design Engineering (Valencia)
🏢 Analog Devices
📍 Valencia