Overview

In this role you will contribute to receiver technology projects, focusing on migrating an architecture from Xilinx MPSoC/FPGA to an ASIC solution. You will shape the target ASIC architecture, implement RTL blocks, and optimize internal interfaces while supporting verification and the overall ASIC flow. You’ll work within the GMV Receivers team on R&D-driven; efforts that aim to deliver new ASIC-based capabilities. This is a hands-on, impact-oriented opportunity at the intersection of hardware architecture and RTL development.

Compensaciones / Beneficios

- Hybrid working model
- 8 weeks per year teleworking
- Adaptable start/finish times
- Intensive Fridays and summer hours
- Personalized career plan development
- language learning support in-house training

Responsabilidades

- Define and evolve the target ASIC architecture
- Develop and adapt RTL blocks (VHDL/Verilog/SystemVerilog)
- Analyze and optimize internal interfaces (buses, memories,



synchronization, clocks, resets)
- Participate in functional verification, simulation, and design debugging
- Contribute to the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT, and design closure
- Document architecture, decisions, and validation results

Requisitos principales

- digital RTL design knowledge
- FPGA, SoC or MPSoC architectures understanding
- internal buses, IP integration, and functional verification experience
- ASIC flow experience including simulation and synthesis tools
- SystemVerilog, UVM, assertions or cocotb (verification)
- embedded ARM/RISC-V and hardware/software partitioning
- experience with Synopsys, Cadence, Siemens EDA, Vivado, or Vitis tools

- VHDL
- Verilog
- SystemVerilog
- RTL design
- FPGA
- SoC/MPSoC architectures

📌 ASIC Design Engineer (Tres Cantos)
🏢 GMV
📍 Tres Cantos